1. Field
Exemplary embodiments of the present invention relate to an integrated circuit and a clock data recovery circuit, and more particularly, to a technology for reducing bang-bang errors.
2. Description of the Related Art
Bang-bang errors often occur in comparators and feedback-based integrated circuits that process comparator results and feed the processed results back.
FIG. 1 is a diagram illustrating a feedback-based integrated circuit.
Referring to FIG. 1, the integrated circuit includes a comparator 110, a processing circuit 120, and a feedback unit 130.
The comparator 110 generates an up/down signal UP/DN by comparing a feedback signal FB with a reference signal REF.
The comparator 110 generates an up/down signal UP/DN by comparing voltage levels or phases of the feedback signal FB and that of the reference signal REF.
The processing circuit 120 processes the up/down signal UP/DN and transfers the processed signal to the feedback unit 130. The processing circuit 120 may perform a variety of types of processing, such as filtering noise or converting up/down signals UP/DN into a signal recognizable to the feedback unit 130.
The feedback unit 130 generates the feedback signal FB based on the processed signal of the processing circuit 120. When the up/down signal UP/DN of the comparator 110 is indicative of an up signal, the feedback unit 130 may make the feedback signal FB up based on the processed signal of the processing of the processing circuit 120. When the up/down signal UP/DN is indicative of a down signal, the feedback unit 130 may make the feedback signal FB down based on the processed signal of the processing of the processing circuit 120. The feedback signal FB is the final output value of the integrated circuit and is also fed back to the comparator 110 again.
Many integrated circuits can have the feedback structure described above. For example, a phase locked loop (PLL), a delay locked loop (DLL), and a clock data recovery (CDR) circuit may have such a feedback structure.
As is well known, a PLL includes a phase detector, a loop filter, and a voltage-controlled oscillator. The phase detector corresponds to the comparator 110, the loop filter corresponds to the processing circuit 120, and the voltage-controlled oscillator corresponds to the feedback unit 130. Furthermore, the DLL includes a phase detector, a delay control circuit, a delay circuit, and a replica delay circuit. The phase detector corresponds to the comparator 110, the delay control circuit corresponds to the processing circuit 120, and the delay circuit and the replica delay circuit correspond to the feedback unit 130. Furthermore, the CDR circuit includes a phase detector, a processing circuit such as a filter, and a phase interpolator. The phase detector corresponds to the comparator 110, the processing circuit such as the filter corresponds to the processing circuit 120, and the phase interpolator may correspond to the feedback unit 130.
That is, the integrated circuit of FIG. 1 does not illustrate a specific circuit, but a general circuit having the feedback scheme.
FIG. 2 is a diagram illustrating a bang-bang error generated in the integrated circuit of FIG. 1.
In FIG. 2, “UP” is indicative of the up signal of the up/down signal UP/DN provided from the comparator 110, and “DN” is indicative of the down signal of the up/down signal UP/DN provided from the comparator 110. In this patent document, 5 cycles are taken as an example for the processing circuit 120 to process the up/down signal UP/DN and to transfer the processed signal to the feedback unit 130. That is, it takes 5 cycles for a result of the comparison of the comparator 110 to be incorporated into the feedback signal FB.
For example, referring to FIG. 2, the voltage level of the feedback signal FB is lower than that of the reference signal REF for 4 cycles from a time point 201. Accordingly, the up/down signal UP/DN of the comparator 110 is indicative of the up signal requiring a rise in the voltage level of the feedback signal FB.
The voltage level of the feedback signal FB becomes higher than that of the reference signal REF from a time point 202. Accordingly, the up/down signal UP/DN of the comparator 110 is indicative of the down signal requiring drop in the voltage level of the feedback signal FB. The voltage level of the feedback signal FB is supposed to be lowered from the time point 202 at which the up/down signal UP/DN is indicative of the down signal. However, the voltage level of the feedback signal FB starts lowering at time point 203 because it takes 5 cycles for the down signal at the time point 202 to be incorporated into the feedback signal FB.
For example, the voltage level of the feedback signal FB becomes lower than that of the reference signal REF from a time point 204. Accordingly the up/down signal UP/DN of the comparator 110 is indicative of the up signal requiring rise in the voltage level of the feedback signal FB. The voltage level of the feedback signal FB is supposed to be raised from the time point 204 at which the up/down signal UP/DN is indicative of the up signal. However, the voltage level of the feedback signal FB starts rising at a time point 205 because it takes 5 cycles for the up signal at the time point 204 to be incorporated into the feedback signal FB.
As described above, the bang-bang error is generated due to the time taken for the comparison result UP/DN of the comparator 110 to be incorporated into the feedback signal FB. In FIG. 2, reference number “210” is indicative of the size of the bang-bang error.
A bang-bang error is generated in almost all the integrated circuits having the feedback structure. In order to improve accuracy in the operation of an integrated circuit, it is very important to reduce bang-bang errors.